1. Field of the Invention
The present invention relates to solid state devices of the type employing a large number of semiconductor devices in an integrated circuit chip. More particularly, the present invention relates to circuits for protecting such semiconductor devices from damaging pulses originating on integrated circuit chip power rail pads.
2. Description of the Prior Art and Related Information
Electrostatic discharge (ESD) is an increasingly significant problem in integrated circuit design. Such potentially destructive electrostatic pulses are due to various transient sources such as human or machine handling of the integrated circuit chip during processing, assembly and installation of the chip. Such ESD events will typically originate at one or more of the integrated circuit electrical contact pads with the specific discharge path varying with the integrated circuit design and the size and polarity of the electrostatic charge applied to the pad. Increased device packing densities and diminished device geometries in modern VLSI chips have generally increased the susceptibility to damage from ESD pulses. Having effective on-chip protection against ESD is very important because elaborate and expensive environmental controls can then be avoided when the integrated circuit is being handled by human operators and assembly machines.
The majority of ESD protection circuits are directed to protection of devices coupled to the IC input/output pads. However, to provide complete protection of the chip, internal devices must also be protected against surges on the IC power pads. That is, the electrostatic pulses need to be allowed to discharge between the positive power pad and the negative power pad without causing any damage to devices interior to the IC. Furthermore, in the case of CMOS (complimentary metal oxide semiconductor) integrated circuits, because of the parasitic diodes usually associated with input/output buffers, an electrostatic pulse applied to an input/output buffer may also cause an ESD pulse between the positive and negative power rails. Moreover, lightning events and other electrical surges, that can occur when the integrated circuit chip has already been inserted into a system, can cause serious damage if the chip does not have adequate protection between the power rails.
One prior art approach to protection against internal damage is to rely merely on the internal parasitic SCR (silicon controlled rectifier) that is always present in CMOS integrated circuits. See, for example, "Electrostatic Discharge: Mechanisms, Protection Techniques, and Effects on Integrated Circuit Reliability", L. R. Avery, RCA Review, June, 1984; and "Internal Chip ESD Phenomena Beyond the Protection Circuit", C. Duvvury, et al. p. 19, 1988 IRPS Proceedings. Referring to FIGS. 1(a), 1(b) and 1(c), such a parasitic SCR present in a CMOS inverter is illustrated. More specifically, in FIG. 1(a), a schematic drawing of a CMOS inverter is shown, and, in FIG. 1(b) a cross-section through an IC incorporating the inverter is illustrated. Also, shown in FIG. 1(b) is a schematic drawing of the parasitic SCR present in the CMOS inverter structure, which schematic is also shown in FIG. 1(c) for clarity. The parasitic SCR 1 thus includes a parasitic pnp bipolar transistor 2 and a parasitic npn bipolar transistor 3, effectively coupled as illustrated in FIG. 1(c). The effective resistance of the n well region and p- epitaxial layers are illustrated schematically as resistors r.sub.n and r.sub.p, respectively.
The SCR 1 will be triggered when a positive pulse is applied to v.sub.DD with respect to V.sub.ss. The parasitic SCR 1 will thus latch into an on state and conduct ESD current from V.sub.DD to V.sub.SS until the ESD pulse ends. (For a negative pulse, the forward biased diode would turn on and serve as a harmless discharge path.) If the characteristics of each of these parasitic structures on the chip are similar, the ESD current will be distributed evenly, and the current density through each one will be small enough that no damage will occur. However, if any of these parasitic SCR structures is particularly more likely to conduct than the others, the current density through it may be high enough to cause damage. Indeed, in some cases melting of the silicon of the IC may occur due to the extreme current which may be drawn through a single SCR. Also, this problem is exacerbated for modern device geometries. That is, the effective resistances r and r.sub.p vary with the dimensions of the device and for modern very small devices these resistances may be high enough to cause significant heating even for less extreme current densities. Furthermore, in modern processes utilizing epitaxial materials, the parasitic SCR becomes much weaker and cannot serve as an efficient discharge path.
Another prior art approach to protection of internal devices from ESD pulses on IC power rails employs an NMOS thick oxide device coupled between V.sub.DD and V.sub.ss. Such a thick oxide device 4 is shown in FIG. 2. For a large positive pulse applied to V.sub.DD, the thick oxide device will conduct in the MOSFET mode and then, shortly afterwards, conduct in a bipolar mode. While this type of device may provide good protection if designed properly, for certain fabrication processes the necessary design constraints for good protection will be incompatible with normal operation of the remainder of the IC. For example, the thick oxide device's threshold voltage may need to be made very high to ensure that the thick oxide device 4 will not turn on during normal IC operation. In such cases, the thick oxide device 4 will not be able to turn on until it enters avalanche breakdown, which turn on mode may not occur quickly enough during an ESD event to prevent damage. In such case a parasitic SCR may turn on first drawing extremely high current as noted above and possibly destroying the IC before the thick oxide device turns on.
Accordingly, a need presently exists for an improved integrated circuit design which provides increased resistance to internal chip damage due to ESD pulses applied to the power rail of the chip.